[all-commits] [llvm/llvm-project] 286198: [InstCombine] Optimize lshr+shl+and conversion pat...

[chenglin.bi via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 286198ff043afa7626705fb69c3e9b8873193573
      https://github.com/llvm/llvm-project/commit/286198ff043afa7626705fb69c3e9b8873193573
  Author: chenglin.bi <chenglin.bi at cixcomputing.com>
  Date:   2022-06-14 (Tue, 14 Jun 2022)

  Changed paths:
    M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
    M llvm/test/Transforms/InstCombine/and.ll

  Log Message:
  -----------
  [InstCombine] Optimize lshr+shl+and conversion pattern

if `C1` and `C3` are pow2 and `Log2(C3) >= C2`:
    ((C1 >> X) << C2) & C3 -> X == (Log2(C1)+C2-Log2(C3)) ? C3 : 0
https://alive2.llvm.org/ce/z/zvrkKF

Reviewed By: spatel

Differential Revision: https://reviews.llvm.org/D127469