[all-commits] [llvm/llvm-project] cb9ae9: [AMDGPU] Define SGPR_NULL64 register. NFCI.
Stanislav Mekhanoshin via All-commits
all-commits at lists.llvm.org
Mon Jun 13 13:23:53 PDT 2022
Author: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Date: 2022-06-13 (Mon, 13 Jun 2022)
[AMDGPU] Define SGPR_NULL64 register. NFCI.
On gfx10+ null register can be used as both 32 and 64 bit operand.
Define a 64 bit version of the register to use during codegen.
Differential Revision: https://reviews.llvm.org/D127527
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