[all-commits] [llvm/llvm-project] 0f6f42: Revert "[RISCV] Add vread_csr and vwrite_csr to ri...

[Wang Pengcheng via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0f6f4295d10fe8cc9c3933b85dc9a66b840e3eca
      https://github.com/llvm/llvm-project/commit/0f6f4295d10fe8cc9c3933b85dc9a66b840e3eca
  Author: wangpc <pc.wang at linux.alibaba.com>
  Date:   2022-06-13 (Mon, 13 Jun 2022)

  Changed paths:
    M clang/include/clang/Basic/riscv_vector.td
    R clang/test/CodeGen/RISCV/rvv-intrinsics/vread-csr.c
    R clang/test/CodeGen/RISCV/rvv-intrinsics/vwrite-csr.c

  Log Message:
  -----------
  Revert "[RISCV] Add vread_csr and vwrite_csr to riscv_vector.h"

This reverts commit aebe24a856d2f40284d940970d4e159319dbb90f.

`REQUIRES` for RISCV target is needed in tests.