[all-commits] [llvm/llvm-project] aebe24: [RISCV] Add vread_csr and vwrite_csr to riscv_vect...

[Wang Pengcheng via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: aebe24a856d2f40284d940970d4e159319dbb90f
      https://github.com/llvm/llvm-project/commit/aebe24a856d2f40284d940970d4e159319dbb90f
  Author: wangpc <pc.wang at linux.alibaba.com>
  Date:   2022-06-13 (Mon, 13 Jun 2022)

  Changed paths:
    M clang/include/clang/Basic/riscv_vector.td
    A clang/test/CodeGen/RISCV/rvv-intrinsics/vread-csr.c
    A clang/test/CodeGen/RISCV/rvv-intrinsics/vwrite-csr.c

  Log Message:
  -----------
  [RISCV] Add vread_csr and vwrite_csr to riscv_vector.h

These two functions are described in RVV intrinsics doc
to read/write RVV CSRs. This matches what GCC does.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D125875