[all-commits] [llvm/llvm-project] c42a22: [MachineScheduler] Order more stores by ascending ...

[Allen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c42a225545b4b494db7866d5db90255926059bc3
      https://github.com/llvm/llvm-project/commit/c42a225545b4b494db7866d5db90255926059bc3
  Author: zhongyunde <zhongyunde at huawei.com>
  Date:   2022-06-13 (Mon, 13 Jun 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64.td
    M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.h
    M llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
    M llvm/lib/Target/AArch64/AArch64MachineScheduler.cpp

  Log Message:
  -----------
  [MachineScheduler] Order more stores by ascending address

According D125377, we order STP Q's by ascending address. While on some
targets, paired 128 bit loads and stores are slow, so the STP will split
into STRQ and STUR, so I hope these stores will also be ordered.
Also add subtarget feature ascend-store-address to control the aggressive order.

Reviewed By: dmgreen, fhahn

Differential Revision: https://reviews.llvm.org/D126700