[all-commits] [llvm/llvm-project] 1cf9b2: [DAG] Enable ISD::FSHL/R SimplifyMultipleUseDemand...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1cf9b24da3b8eb8e7636de2209f192ded5ce20cd
      https://github.com/llvm/llvm-project/commit/1cf9b24da3b8eb8e7636de2209f192ded5ce20cd
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2022-06-12 (Sun, 12 Jun 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/test/CodeGen/PowerPC/urem-seteq-illegal-types.ll
    M llvm/test/CodeGen/X86/clear_upper_vector_element_bits.ll
    M llvm/test/CodeGen/X86/const-shift-of-constmasked.ll
    M llvm/test/CodeGen/X86/funnel-shift.ll
    M llvm/test/CodeGen/X86/rotate-extract.ll
    M llvm/test/CodeGen/X86/sdiv_fix_sat.ll
    M llvm/test/CodeGen/X86/shift-mask.ll

  Log Message:
  -----------
  [DAG] Enable ISD::FSHL/R SimplifyMultipleUseDemandedBits handling inside SimplifyDemandedBits

This patch allows SimplifyDemandedBits to call SimplifyMultipleUseDemandedBits in cases where the source operand has other uses, enabling us to peek through the shifted value if we don't demand all the bits/elts.

This helps with several of the regressions from D125836