[all-commits] [llvm/llvm-project] a639e1: [RISCV] Add test case showing failure to convert g...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a639e1fceb727a628bc52a064f2a2462fe1a5eaa
      https://github.com/llvm/llvm-project/commit/a639e1fceb727a628bc52a064f2a2462fe1a5eaa
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-06-10 (Fri, 10 Jun 2022)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store-asm.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store.ll

  Log Message:
  -----------
  [RISCV] Add test case showing failure to convert gather/scatter to strided load/store. NFC

Our optimization pass checks for loop simplify form, before doing
the transform. The loops here aren't in loop simplify form because
the exit block has two predecessors.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D127451


  Commit: 08ea27bf13e68afc805b31af27634103dd392c8c
      https://github.com/llvm/llvm-project/commit/08ea27bf13e68afc805b31af27634103dd392c8c
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-06-10 (Fri, 10 Jun 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store-asm.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store.ll

  Log Message:
  -----------
  [RISCV] Don't require loop simplify form in RISCVGatherScatterLowering.

We need a preheader and a single latch, but we don't need a dedicated
exit.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D127513


Compare: https://github.com/llvm/llvm-project/compare/275b2e524363...08ea27bf13e6