[all-commits] [llvm/llvm-project] 91adbc: [DAG] SimplifyDemandedVectorElts - adding Simplify...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 91adbc3208d0ce42550e42237b8d97fb866165a1
      https://github.com/llvm/llvm-project/commit/91adbc3208d0ce42550e42237b8d97fb866165a1
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2022-06-10 (Fri, 10 Jun 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/test/CodeGen/AMDGPU/scalar_to_vector.v8i16.ll
    M llvm/test/CodeGen/X86/pr46820.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-3.ll
    M llvm/test/CodeGen/X86/x86-interleaved-access.ll

  Log Message:
  -----------
  [DAG] SimplifyDemandedVectorElts - adding SimplifyMultipleUseDemandedVectorElts handling to ISD::CONCAT_VECTORS

Attempt to look through multiple use operands of ISD::CONCAT_VECTORS nodes

Another minor improvement for D127115