[all-commits] [llvm/llvm-project] f68cad: [RISCV] Lower VLEFF/VLSEGFF SDNodes to MachineInst...

[Yeting Kuo via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f68cad90870590b7b1854828f255070301873347
      https://github.com/llvm/llvm-project/commit/f68cad90870590b7b1854828f255070301873347
  Author: Yeting Kuo <yeting.kuo at sifive.com>
  Date:   2022-06-10 (Fri, 10 Jun 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/lib/Target/RISCV/RISCVMCInstLower.cpp
    R llvm/test/CodeGen/RISCV/rvv/vleff-rv32-readvl.ll
    R llvm/test/CodeGen/RISCV/rvv/vleff-rv64-readvl.ll
    A llvm/test/CodeGen/RISCV/rvv/vleff-vlseg2ff-output.ll
    R llvm/test/CodeGen/RISCV/rvv/vlseg2ff-rv32-readvl.ll
    R llvm/test/CodeGen/RISCV/rvv/vlseg2ff-rv64-readvl.ll
    M llvm/test/CodeGen/RISCV/rvv/vmv-copy.mir

  Log Message:
  -----------
  [RISCV] Lower VLEFF/VLSEGFF SDNodes to MachineInstrs with VL outputs.

The patch is a replacement of D125199. PseudoReadVL with vtype has worry for
computing same vtypes of VLEFF/VLSEGFF in two different places, DAGToDAG and
InsertVSETVLI. VLEFF/VLSEGFF MI with VL output still could provide the vtype of
VLEFF/VLSEGFF to the users of its VL.

The patch names the new pseudo as original VLEFF/VLSEGFF name suffixed "_VL" and
expand them in RISCVInsertVSETVLI pass.

This patch also reverts commit 4537aae0d57e17c217c192d8977012ba475b130c,
"[RISCV] Make PseudoReadVL have the vtypes of the corresponding VLEFF/VLSEGFF.".

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D126794