[all-commits] [llvm/llvm-project] de7a6a: [InstCombine] Optimize shl+lshr+and conversion pa...

[chenglin.bi via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: de7a6ae1ffc36baa16188d3dd5befa385d05700d
      https://github.com/llvm/llvm-project/commit/de7a6ae1ffc36baa16188d3dd5befa385d05700d
  Author: chenglin.bi <chenglin.bi at cixcomputing.com>
  Date:   2022-06-10 (Fri, 10 Jun 2022)

  Changed paths:
    M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
    M llvm/test/Transforms/InstCombine/and.ll
    M llvm/test/Transforms/InstCombine/icmp-and-shift.ll

  Log Message:
  -----------
   [InstCombine] Optimize shl+lshr+and conversion pattern

if `C1` and `C3` are pow2 and `Log2(C3)+C2 < BitWidth`:
    ((C1 << X) >> C2) & C3 -> X == (Log2(C3)+C2-Log2(C1)) ? C3 : 0;

https://alive2.llvm.org/ce/z/Pus5bd

Fix issue https://github.com/llvm/llvm-project/issues/55739

Reviewed By: spatel

Differential Revision: https://reviews.llvm.org/D126617