[all-commits] [llvm/llvm-project] 8bbcb9: [RISCV] Teach RISCVMergeBaseOffset about cases whe...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8bbcb988481c4b072e5f545ef222078ff2a8df3b
      https://github.com/llvm/llvm-project/commit/8bbcb988481c4b072e5f545ef222078ff2a8df3b
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-06-09 (Thu, 09 Jun 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
    M llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll

  Log Message:
  -----------
  [RISCV] Teach RISCVMergeBaseOffset about cases where we use SHXADD to add some immediates.

For an addition with simm14 and simm15 immediates with 2 or 3 trailing bits,
we can use a shXadd instruction and an addi to do the addition.

This patch teaches RISCVMergeBaseOffset to see through this pattern.
I don't think the sh1add case occurs because we use two addis for that,
but I implemented it for completeness.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D127376