[all-commits] [llvm/llvm-project] 7dbfcf: [DAG] combineInsertEltToShuffle - if EXTRACT_VECTO...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7dbfcfa735f28a3bd33b465c686a20c4974373ae
      https://github.com/llvm/llvm-project/commit/7dbfcfa735f28a3bd33b465c686a20c4974373ae
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2022-06-09 (Thu, 09 Jun 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-6.ll

  Log Message:
  -----------
  [DAG] combineInsertEltToShuffle - if EXTRACT_VECTOR_ELT fails to match an existing shuffle op, try to replace an undef op if there is one.

This should fix a number of shuffle regressions in D127115 where the re-ordered combines mean we fail to fold a EXTRACT_VECTOR_ELT/INSERT_VECTOR_ELT sequence into a BUILD_VECTOR if we extract from more than one vector source.