[all-commits] [llvm/llvm-project] 6a6f63: Revert "[RISCV] Testcase to show wrong register al...

[Kito Cheng via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6a6f632b93cd3ed9e35f37c04efb12fa87038b60
      https://github.com/llvm/llvm-project/commit/6a6f632b93cd3ed9e35f37c04efb12fa87038b60
  Author: Kito Cheng <kito.cheng at sifive.com>
  Date:   2022-06-08 (Wed, 08 Jun 2022)

  Changed paths:
    R llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll
    R llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.mir

  Log Message:
  -----------
  Revert "[RISCV] Testcase to show wrong register allocation result of subreg liveness"

Revert due to failed on LLVM_ENABLE_EXPENSIVE_CHECKS.

This reverts commit cbe22c794348a1962af8a5d21fbedbb65974d94c.