[all-commits] [llvm/llvm-project] e243ea: Reland [AMDGPU] gfx11 vop3dpp instructions

[Joe Nash via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e243ead6fc0af016bb8863fff3687a52afc20e61
      https://github.com/llvm/llvm-project/commit/e243ead6fc0af016bb8863fff3687a52afc20e61
  Author: Joe Nash <Joseph.Nash at amd.com>
  Date:   2022-06-07 (Tue, 07 Jun 2022)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPU.td
    M llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
    M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
    M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
    M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
    M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
    M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.h
    M llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
    M llvm/lib/Target/AMDGPU/SIDefines.h
    M llvm/lib/Target/AMDGPU/SIInstrFormats.td
    M llvm/lib/Target/AMDGPU/SIInstrInfo.td
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
    M llvm/lib/Target/AMDGPU/VOP2Instructions.td
    M llvm/lib/Target/AMDGPU/VOP3Instructions.td
    M llvm/lib/Target/AMDGPU/VOPInstructions.td
    A llvm/test/MC/AMDGPU/gfx11_asm_dpp.s
    M llvm/test/MC/AMDGPU/gfx11_err.s
    M llvm/test/MC/AMDGPU/gfx9-asm-err.s
    M llvm/test/MC/AMDGPU/vop_dpp.s
    M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_all.txt

  Log Message:
  -----------
  Reland [AMDGPU] gfx11 vop3dpp instructions

There was an issue with encoding wide (>64 bit) instructions on
BigEndian hosts, which is fixed in D127195. Therefore reland this.

gfx11 adds the ability to use dpp modifiers on vop3 instructions.
This patch adds machine code layer support for that. The MCCodeEmitter
is changed to use APInt instead of uint64_t to support these wider
instructions.

Patch 16/N for upstreaming of AMDGPU gfx11 architecture

Differential Revision: https://reviews.llvm.org/D126483