[all-commits] [llvm/llvm-project] bccbf5: [AArch64] Remove isDef32

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: bccbf5276e6ee23a427b48d80ad42ff31575c1e7
      https://github.com/llvm/llvm-project/commit/bccbf5276e6ee23a427b48d80ad42ff31575c1e7
  Author: David Green <david.green at arm.com>
  Date:   2022-06-07 (Tue, 07 Jun 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
    M llvm/test/CodeGen/AArch64/arm64-popcnt.ll
    M llvm/test/CodeGen/AArch64/arm64-shifted-sext.ll
    M llvm/test/CodeGen/AArch64/dp1.ll

  Log Message:
  -----------
  [AArch64] Remove isDef32

isDef32 would attempt to make a guess at which SelectionDag nodes were
32bit sources, and use the nature of 32bit AArch64 instructions
implicitly zeroing the upper register half to not emit zext that were
expected to already be zero. This was a bit fragile though, needing to
guess at the correct opcodes that do not become 32bit defs later in
ISel.

This patch removed isDef32, relying on the AArch64MIPeephole optimizer
to remove redundant SUBREG_TO_REG nodes. A part of
SelectArithExtendedRegister was left with the same logic as a heuristic
to prevent some regressions from it picking less optimal sequences.
The AArch64MIPeepholeOpt pass also needs to be taught that a COPY from a
FPR will become a FMOVSWr, which it lowers immediately to make sure that
remains true through register allocation.

Fixes #55833

Differential Revision: https://reviews.llvm.org/D127154