[all-commits] [llvm/llvm-project] 8956f8: [InstCombine] add vector tests for shift-shift; NFC

[Sanjay Patel via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8956f80e4b57a87995d75153df3eec06d4d4ff05
      https://github.com/llvm/llvm-project/commit/8956f80e4b57a87995d75153df3eec06d4d4ff05
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2022-06-07 (Tue, 07 Jun 2022)

  Changed paths:
    M llvm/test/Transforms/InstCombine/shift-shift.ll

  Log Message:
  -----------
  [InstCombine] add vector tests for shift-shift; NFC

D127122


  Commit: 82040d414b3c9fc283ba57c8193fbc9578044cd9
      https://github.com/llvm/llvm-project/commit/82040d414b3c9fc283ba57c8193fbc9578044cd9
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2022-06-07 (Tue, 07 Jun 2022)

  Changed paths:
    M llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
    M llvm/test/Transforms/InstCombine/shift-shift.ll

  Log Message:
  -----------
  [InstCombine] reduce right-shift-of-left-shifted constant via demanded bits

If we don't demand high bits (zeros) and it is valid to pre-shift a constant:
(C2 << X) >> C1 --> (C2 >> C1) << X

https://alive2.llvm.org/ce/z/P3dWDW

There are a variety of related patterns, but I haven't found a single solution
that gets all of the motivating examples - so pulling this piece out of
D126617 along with more tests.

We should also handle the case where we shift-right followed by shift-left,
but I'll make that a follow-on patch assuming this one is ok. It seems likely
that we would want to add this to the SDAG version of the code too to keep it
on par with IR.

Differential Revision: https://reviews.llvm.org/D127122


Compare: https://github.com/llvm/llvm-project/compare/445e2b2aa069...82040d414b3c