[all-commits] [llvm/llvm-project] 0c66de: [RISCV] Scalarize gather/scatter on RV64 with Zve3...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0c66deb498e6c2389988500b5037d91b81f79ed9
      https://github.com/llvm/llvm-project/commit/0c66deb498e6c2389988500b5037d91b81f79ed9
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-06-07 (Tue, 07 Jun 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
    M llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store-asm.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll

  Log Message:
  -----------
  [RISCV] Scalarize gather/scatter on RV64 with Zve32* extension.

i64 indices aren't supported on Zve32*. Scalarize gathers to prevent
generating illegal instructions.

Since InstCombine will aggressively canonicalize GEP indices to
pointer size, we're pretty much always going to have an i64 index.

Trying to predict when SelectionDAG will find a smaller index from
the TTI hook used by the ScalarizeMaskedMemIntrinPass seems fragile.
To optimize this we probably need an IR pass to rewrite it earlier.

Test RUN lines have also been added to make sure the strided load/store
optimization still works.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D127179