[all-commits] [llvm/llvm-project] 440285: [RISCV] Reduce scalar load/store isel patterns to ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 440285200265eca0e148cb838f83fa7cbc37c640
      https://github.com/llvm/llvm-project/commit/440285200265eca0e148cb838f83fa7cbc37c640
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-06-03 (Fri, 03 Jun 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoA.td

  Log Message:
  -----------
  [RISCV] Reduce scalar load/store isel patterns to a single ComplexPattern. NFCI

Previously we had 3 different isel patterns for every scalar load
store instruction.

This reduces them to a single ComplexPattern that returns the Base
and Offset. Or an offset of 0 if there was no offset identified

I've done a similar thing for the 2 isel patterns that match add/or
with FrameIndex and immediate. Using the offset of 0, I was also
able to remove the custom handler for FrameIndex. Happy to split that
to another patch.

We might be able to enhance in the future to remove the post-isel
peephole or the special handling for ADD with constant added by D126576.

A nice side effect is that this removes nearly 3000 bytes from the isel
table.

Differential Revision: https://reviews.llvm.org/D126932