[all-commits] [llvm/llvm-project] dbead2: [RISCV] Add custom isel for (add X, imm) used by l...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: dbead2388b48c1730f54f9aef074a81254573797
      https://github.com/llvm/llvm-project/commit/dbead2388b48c1730f54f9aef074a81254573797
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-06-02 (Thu, 02 Jun 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/test/CodeGen/RISCV/mem.ll
    M llvm/test/CodeGen/RISCV/mem64.ll
    M llvm/test/CodeGen/RISCV/split-offsets.ll

  Log Message:
  -----------
  [RISCV] Add custom isel for (add X, imm) used by load/stores.

If the imm is out of range for an ADDI, we will materialize it in
a register using multiple instructions. If the ADD is used by a
load/store, doPeepholeLoadStoreADDI can try to pull an ADDI from
the constant materialization into the load/store offset. This only
works if the ADD has a single use, otherwise the peephole would have
to rebuild multiple nodes.

This patch instead tries to solve the problem when the add is selected.
We check that the add is only used by loads/stores and if it is
we will select it to (ADDI (ADD X, Imm-Lo12), Lo12). This will enable
the simple case in doPeepholeLoadStoreADDI that can bypass an ADDI
used as a pointer. As a result we can remove the more complicated
peephole from doPeepholeLoadStoreADDI.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D126576