[all-commits] [llvm/llvm-project] fa20bf: [DAGCombiner][RISCV] Improve computeKnownBits for ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: fa20bf1636a8f3cbcbabcf6cdc21a817935201f7
      https://github.com/llvm/llvm-project/commit/fa20bf1636a8f3cbcbabcf6cdc21a817935201f7
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-06-02 (Thu, 02 Jun 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/test/CodeGen/RISCV/min-max.ll

  Log Message:
  -----------
  [DAGCombiner][RISCV] Improve computeKnownBits for (smax X, C) where C is non-negative.

If C is non-negative, the result of the smax must also be
non-negative, so all sign bits of the result are 0.

This allows DAGCombiner to remove a zext_inreg in the modified test.
This zext_inreg started as a sext that became zext before type
legalization then was promoted to a zext_inreg.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D126896