[all-commits] [llvm/llvm-project] 01ba47: [RISCV] Add test case showing unnecessary extend a...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 01ba470826a84a8d73e88916605b838bb962f52a
      https://github.com/llvm/llvm-project/commit/01ba470826a84a8d73e88916605b838bb962f52a
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-06-02 (Thu, 02 Jun 2022)

  Changed paths:
    M llvm/test/CodeGen/RISCV/min-max.ll

  Log Message:
  -----------
  [RISCV] Add test case showing unnecessary extend after i32 smax on rv64. NFC

One of the operands of the smax is a positive value so computeKnownBits
determines the result of the smax must always be positive. This allows
DAG combiner to convert the sign extend to zero extend before type
legalization.

After type legalization the smax is promoted to i64 by sign extending
its inputs and the zero extend becomes an AND instruction. We are unable
to remove the AND at this point and it becomes a pair of shifts or a
zext.w.

The result of smax has as many sign bits as the minimum of its inputs.
Had we kept the sign extend instead of turning it into a zero extend
it would be removed by DAG combiner after type legalization.