[all-commits] [llvm/llvm-project] dcdb0b: [RISCV] Fix an inconsistency with compatible load/...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: dcdb0bf25bc83e4ae4e7da87311dd93030e9c9ce
      https://github.com/llvm/llvm-project/commit/dcdb0bf25bc83e4ae4e7da87311dd93030e9c9ce
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2022-06-02 (Thu, 02 Jun 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir

  Log Message:
  -----------
  [RISCV] Fix an inconsistency with compatible load/store handling

Once we've computed the incoming predecessor state, we should use the same compatibility check with knowledge of MI as we did in phase 2 in order to be consistent across all phases.

Differential Revision: https://reviews.llvm.org/D126574