[all-commits] [llvm/llvm-project] f15add: [RISCV] Split fixed-vector-strided-load-store.ll s...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f15add7d93aeabbfa381499a04eae769cc1cf4f0
      https://github.com/llvm/llvm-project/commit/f15add7d93aeabbfa381499a04eae769cc1cf4f0
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2022-06-01 (Wed, 01 Jun 2022)

  Changed paths:
    A llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store-asm.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store.ll

  Log Message:
  -----------
  [RISCV] Split fixed-vector-strided-load-store.ll so it can be autogened

I've gotten tired of updating register allocation changes by hand, let's just autogen this even if we have to duplicate it.