[all-commits] [llvm/llvm-project] aeb27f: [RISCV] Fix i64<->f64 and i32<->f32 bitcasts with ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: aeb27f133af224f4899998586e8f9d0f7dc0c907
      https://github.com/llvm/llvm-project/commit/aeb27f133af224f4899998586e8f9d0f7dc0c907
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-06-01 (Wed, 01 Jun 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll

  Log Message:
  -----------
  [RISCV] Fix i64<->f64 and i32<->f32 bitcasts with VLS vectors enabled.

We enable a custom handler to optimize conversions between scalars
and fixed vectors. Unfortunately, the custom handler picks up scalar
to scalar conversions as well. If the scalar types are both legal,
we wouldn't match any of the fixed vector cases and would return SDValue()
causing the LegalizeDAG to expand the bitcast through memory.

This patch fixes this by checking if it's a scalar to scalar conversion
and returns `Op` if both types are legal.

Differential Revision: https://reviews.llvm.org/D126739