[all-commits] [llvm/llvm-project] 2e61df: [AMDGPU] Instruction Type Pipeline

[Jeffrey Byrnes via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2e61dfb1249e80a36a611c889f3ef86fa4cf3c85
      https://github.com/llvm/llvm-project/commit/2e61dfb1249e80a36a611c889f3ef86fa4cf3c85
  Author: jeff <jrbyrnes1989 at gmail.com>
  Date:   2022-05-31 (Tue, 31 May 2022)

  Changed paths:
    R llvm/lib/Target/AMDGPU/AMDGPUMFMAClustering.cpp
    R llvm/lib/Target/AMDGPU/AMDGPUMFMAClustering.h
    A llvm/lib/Target/AMDGPU/AMDGPUMFMAIGroupLP.cpp
    A llvm/lib/Target/AMDGPU/AMDGPUMFMAIGroupLP.h
    M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
    M llvm/lib/Target/AMDGPU/CMakeLists.txt
    R llvm/test/CodeGen/AMDGPU/mfma-cluster-edges.mir
    R llvm/test/CodeGen/AMDGPU/mfma-cluster.mir
    A llvm/test/CodeGen/AMDGPU/mfma-igrouplp-dag-mutation.mir

  Log Message:
  -----------
  [AMDGPU] Instruction Type Pipeline

This patch implements a DAG mutation which adds edges between different groups of instructions. The purpose is to try to generate code that conforms to a pipeline (groupA instructions occur before groupB, groupB -> groupC, and so on). Currently the pipeline order is hardcoded as VMEM->DSRead->MFMA->DSWrite, but the patch was designed to be easily extensible. Alias analysis is problematic for pipelining as memory instructions will usually not be able to be reordered w.r.t one another.

Differential Revision: https://reviews.llvm.org/D125997