[all-commits] [llvm/llvm-project] 3b5456: [RISCV] Pre-commit tests for D126635. NFC

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3b5456d5f0d1fbfcdf6f6a18e9adec5e42a560ee
      https://github.com/llvm/llvm-project/commit/3b5456d5f0d1fbfcdf6f6a18e9adec5e42a560ee
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-05-31 (Tue, 31 May 2022)

  Changed paths:
    M llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll

  Log Message:
  -----------
  [RISCV] Pre-commit tests for D126635. NFC


  Commit: 80c4cf6369459f90e103339fcb9f6767474f478b
      https://github.com/llvm/llvm-project/commit/80c4cf6369459f90e103339fcb9f6767474f478b
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-05-31 (Tue, 31 May 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
    M llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll

  Log Message:
  -----------
  [RISCV] Fix a few corner case bugs in RISCVMergeBaseOffsetOpt::matchLargeOffset

The immediate for LUI is stored as 20-bit unsigned value. We need
to sign extend if after shifting by 12 to match the instruction
behavior.

If we find an LUI+ADDI on RV64, it means the constant isn't a
simm32. If it was, we would have emitted LUI+ADDIW from constant
materialization. Make sure the constant is a simm32 before folding.
This appears to match gcc.

A future patch will add support for LUI+ADDIW on RV64.


Compare: https://github.com/llvm/llvm-project/compare/2bf6123f22c6...80c4cf636945