[all-commits] [llvm/llvm-project] e642d0: [RISCV] Add test cases showing missed opportunity ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e642d0ea215897993f925661d53b9091fa2bcc6e
      https://github.com/llvm/llvm-project/commit/e642d0ea215897993f925661d53b9091fa2bcc6e
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-05-29 (Sun, 29 May 2022)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rv64zba.ll

  Log Message:
  -----------
  [RISCV] Add test cases showing missed opportunity to use shXadd.uw. NFC

The tests here show the codegen for something like this C code.

unsigned diff = ptr1 - ptr2;
return ptr3[diff];

The pointer difference is truncated to 32-bits before being used
again as an index. In SelectionDAG this appears as an AND between
a SRL and a SHL. DAGCombiner will remove the shifts leaving only
an AND. The Mask now has 1,2, or 3 trailing zeros and 31, 30, or 29
leading zeros. We end up falling back to constant materialization
to create this mask.

We could instead use srli followed by slli.uw. Or since
we have an add, we can use srli followed by shXadd.uw.

Differential Revision: https://reviews.llvm.org/D126589


  Commit: 6a6cf2e28db5ef2451c117c7896208091da5d2a0
      https://github.com/llvm/llvm-project/commit/6a6cf2e28db5ef2451c117c7896208091da5d2a0
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-05-29 (Sun, 29 May 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
    M llvm/test/CodeGen/RISCV/rv64zba.ll

  Log Message:
  -----------
  [RISCV] isel (add (and X, 0x1FFFFFFFE), Y) as (SH1ADD (SRLI X, 1), Y)

This pattern is what we get after DAG combine for C code like this.

short *ptr1, *ptr2, *ptr3;
unsigned diff = ptr1 - ptr2;
return ptr3[diff];

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D126588


Compare: https://github.com/llvm/llvm-project/compare/0776c48f9b7e...6a6cf2e28db5