[all-commits] [llvm/llvm-project] 85b447: [RISCV] Allow PRE of vsetvli involving non-1 LMUL

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 85b4470035b74834dcba3be14e8abb530f302caa
      https://github.com/llvm/llvm-project/commit/85b4470035b74834dcba3be14e8abb530f302caa
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2022-05-27 (Fri, 27 May 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
    M llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll

  Log Message:
  -----------
  [RISCV] Allow PRE of vsetvli involving non-1 LMUL

This is a follow up to address a review comment from D124869. When deciding whether to PRE a vsetvli, we can allow non-LMUL1 vsetvlis.

Differential Revision: https://reviews.llvm.org/D126563