[all-commits] [llvm/llvm-project] aaad50: [RISCV] Return false from isOffsetFoldingLegal ins...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: aaad507546a5cc788aabc907ec47bbbfb8283e8e
      https://github.com/llvm/llvm-project/commit/aaad507546a5cc788aabc907ec47bbbfb8283e8e
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-05-27 (Fri, 27 May 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/test/CodeGen/RISCV/double-mem.ll
    M llvm/test/CodeGen/RISCV/float-mem.ll
    M llvm/test/CodeGen/RISCV/half-mem.ll
    M llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll
    M llvm/test/CodeGen/RISCV/loop-strength-reduce-add-cheaper-than-mul.ll
    M llvm/test/CodeGen/RISCV/loop-strength-reduce-loop-invar.ll
    M llvm/test/CodeGen/RISCV/mem.ll
    M llvm/test/CodeGen/RISCV/mem64.ll
    M llvm/test/CodeGen/RISCV/zext-with-load-is-free.ll

  Log Message:
  -----------
  [RISCV] Return false from isOffsetFoldingLegal instead of reversing the fold in lowering.

When lowering GlobalAddressNodes, we were removing a non-zero offset and
creating a separate ADD.

It already comes out of SelectionDAGBuilder with a separate ADD. The
ADD was being removed by DAGCombiner.

This patch disables the DAG combine so we don't have to reverse it.
Test changes all look to be instruction order changes. Probably due
to different DAG node ordering.

Differential Revision: https://reviews.llvm.org/D126558