[all-commits] [llvm/llvm-project] 8a3b6b: [RISCV] Add a subtarget feature to enable unaligne...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8a3b6ba7569e80782dbd1893902bd6134bd6ff01
      https://github.com/llvm/llvm-project/commit/8a3b6ba7569e80782dbd1893902bd6134bd6ff01
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2022-05-26 (Thu, 26 May 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCV.td
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVSubtarget.h
    M llvm/test/CodeGen/RISCV/unaligned-load-store.ll

  Log Message:
  -----------
  [RISCV] Add a subtarget feature to enable unaligned scalar loads and stores

A RISCV implementation can choose to implement unaligned load/store support. We currently don't have a way for such a processor to indicate a preference for unaligned load/stores, so add a subtarget feature.

There doesn't appear to be a formal extension for unaligned support. The RISCV Profiles (https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#rva20u64-profile) docs use the name Zicclsm, but a) that doesn't appear to actually been standardized, and b) isn't quite what we want here anyway due to the perf comment.

Instead, we can follow precedent from other backends and have a feature flag for the existence of misaligned load/stores with sufficient performance that user code should actually use them.

Differential Revision: https://reviews.llvm.org/D126085