[all-commits] [llvm/llvm-project] 18cb3b: [ARM] Fix vcvtb/t.f16 input liveness

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 18cb3b35066e5f385fa08d373c60447a3aa88ce3
      https://github.com/llvm/llvm-project/commit/18cb3b35066e5f385fa08d373c60447a3aa88ce3
  Author: David Green <david.green at arm.com>
  Date:   2022-05-25 (Wed, 25 May 2022)

  Changed paths:
    M llvm/lib/Target/ARM/ARMInstrFormats.td
    M llvm/lib/Target/ARM/ARMInstrVFP.td
    M llvm/test/CodeGen/ARM/aes-erratum-fix.ll
    M llvm/test/CodeGen/Thumb2/mve-div-expand.ll
    M llvm/test/CodeGen/Thumb2/mve-fmath.ll
    M llvm/test/CodeGen/Thumb2/mve-masked-store.ll
    M llvm/test/CodeGen/Thumb2/mve-vcvt.ll
    M llvm/test/CodeGen/Thumb2/mve-vcvt16.ll

  Log Message:
  -----------
  [ARM] Fix vcvtb/t.f16 input liveness

The `vcvtb.f16.f32 Sd, Sn` (and vcvtt.f16.f32) instruction convert a f32
into a f16, writing either the top or bottom halves of the register.
That means that half of the input register Sd is used in the output.
This wasn't being modelled in the instructions, leading later analyses
to believe that the registers were dead where they were not, generating
invalid scheduling

Fix that be specifying the input Sda register for the instructions too,
allowing them to be set for cases like vector inserts. Most of the
changes are plumbing through the constraint string, cstr.

Differential Revision: https://reviews.llvm.org/D126118