[all-commits] [llvm/llvm-project] 948d93: [RISCV] Ensure the forwarded AVL register is alive

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 948d931323a13dfc68430814a44b9075a59e2310
      https://github.com/llvm/llvm-project/commit/948d931323a13dfc68430814a44b9075a59e2310
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2022-05-24 (Tue, 24 May 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll

  Log Message:
  -----------
  [RISCV] Ensure the forwarded AVL register is alive

When the AVL value does not fit in 5 bits, the register in which this value is stored may be dead when we want to forward it. This patch ensure the kill flags on the register are cleared before forwarding.

Patch by: loralb
Differential Revision: https://reviews.llvm.org/D125971