[all-commits] [llvm/llvm-project] a95ecb: [RISCV] Hoist VSETVLI out of idiomatic fixed lengt...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a95ecb20bca894cc1373a85360ad5939dd2c3ff9
      https://github.com/llvm/llvm-project/commit/a95ecb20bca894cc1373a85360ad5939dd2c3ff9
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2022-05-24 (Tue, 24 May 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store.ll
    M llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll

  Log Message:
  -----------
  [RISCV] Hoist VSETVLI out of idiomatic fixed length vector loops

This patch teaches the VSETVLI insertion pass to perform a very limited form of partial redundancy elimination. The motivating example comes from the fixed length vectorization of a simple loop such as:

for (unsigned i = 0; i < a_len; i++)
    a[i] += b;

Without this change, the core vector loop and preheader is as follows:

.LBB0_3:                                # %vector.ph
	andi	a1, a6, -8
	addi	a4, a0, 16
	mv	a5, a1
.LBB0_4:                                # %vector.body
                                        # =>This Inner Loop Header: Depth=1
	addi	a3, a4, -16
	vsetivli	zero, 4, e32, m1, ta, mu
	vle32.v	v8, (a3)
	vle32.v	v9, (a4)
	vadd.vx	v8, v8, a2
	vadd.vx	v9, v9, a2
	vse32.v	v8, (a3)
	vse32.v	v9, (a4)
	addi	a5, a5, -8
	addi	a4, a4, 32
	bnez	a5, .LBB0_4

The key thing to note here is that, the execution of the vsetivli only needs to happen once. Since there's no tail folding happening here, the value of the vector configuration registers are invariant through the loop.

After this patch, we hoist the configuration into the preheader and perform it once.

.LBB0_3:                                # %vector.ph
	andi	a1, a6, -8
	vsetivli	zero, 4, e32, m1, ta, mu
	addi	a4, a0, 16
	mv	a5, a1
.LBB0_4:                                # %vector.body
                                        # =>This Inner Loop Header: Depth=1
	addi	a3, a4, -16
	vle32.v	v8, (a3)
	vle32.v	v9, (a4)
	vadd.vx	v8, v8, a2
	vadd.vx	v9, v9, a2
	vse32.v	v8, (a3)
	vse32.v	v9, (a4)
	addi	a5, a5, -8
	addi	a4, a4, 32
	bnez	a5, .LBB0_4

Differential Revision: https://reviews.llvm.org/D124869


  Commit: fb948572e03321b1470a2e47fbf685226f8f5f18
      https://github.com/llvm/llvm-project/commit/fb948572e03321b1470a2e47fbf685226f8f5f18
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2022-05-24 (Tue, 24 May 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

  Log Message:
  -----------
  [riscv] Use getFirstInstrTerminator [nfc]


Compare: https://github.com/llvm/llvm-project/compare/6f215ca680fd...fb948572e033