[all-commits] [llvm/llvm-project] cddeb7: [RISCV] Add test cases showing failure to remove m...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: cddeb78e8d5b7b924c920fb702d3d883b2661b12
      https://github.com/llvm/llvm-project/commit/cddeb78e8d5b7b924c920fb702d3d883b2661b12
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-05-24 (Tue, 24 May 2022)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rotl-rotr.ll

  Log Message:
  -----------
  [RISCV] Add test cases showing failure to remove mask on rotate amounts.

This is similar to tests I added in
e2f410feeab27a8bb2c015fc02bb8527702e401f that had to be reverted.

I've modified them to avoid the bug that is being fixed by D126036.


  Commit: 415b9f595d4d2fae947f86b239777ec54c3824dc
      https://github.com/llvm/llvm-project/commit/415b9f595d4d2fae947f86b239777ec54c3824dc
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-05-24 (Tue, 24 May 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
    M llvm/test/CodeGen/RISCV/rotl-rotr.ll

  Log Message:
  -----------
  Recommit "[RISCV] Use selectShiftMaskXLen ComplexPattern for isel of rotates."

This reverts commit dfe513ae1bb6e788ead93b850d80d77d54cf29d3.

Tests have been changed to avoid the type legalization bug being
fixed in D126036.

Original commit message:
This will remove masks on the shift amount. We usually get this with
SimplifyDemandedBits in DAGCombine, but that's restricted to cases
where the AND has a single use. selectShiftMaskXLen does not have
that restriction.


Compare: https://github.com/llvm/llvm-project/compare/1b976f2cb22f...415b9f595d4d