[all-commits] [llvm/llvm-project] 496156: [X86][AMX] Multiple configure for AMX register.

[Luo, Yuanke via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 496156ac57da3abd9c8a6dc422852b7bdfaa448f
      https://github.com/llvm/llvm-project/commit/496156ac57da3abd9c8a6dc422852b7bdfaa448f
  Author: Luo, Yuanke <yuanke.luo at intel.com>
  Date:   2022-05-24 (Tue, 24 May 2022)

  Changed paths:
    M llvm/lib/Target/X86/CMakeLists.txt
    M llvm/lib/Target/X86/X86.h
    A llvm/lib/Target/X86/X86FastPreTileConfig.cpp
    M llvm/lib/Target/X86/X86FastTileConfig.cpp
    M llvm/lib/Target/X86/X86InstrAMX.td
    M llvm/lib/Target/X86/X86TargetMachine.cpp
    M llvm/test/CodeGen/X86/AMX/amx-across-func.ll
    M llvm/test/CodeGen/X86/AMX/amx-configO0toO0.ll
    M llvm/test/CodeGen/X86/AMX/amx-configO2toO0.ll
    A llvm/test/CodeGen/X86/AMX/amx-fastconfig-phi.mir
    A llvm/test/CodeGen/X86/AMX/amx-fastconfig-phi2.mir
    A llvm/test/CodeGen/X86/AMX/amx-fastconfig-phi4.mir
    A llvm/test/CodeGen/X86/AMX/amx-fastconfig-spill.mir
    A llvm/test/CodeGen/X86/AMX/amx-fastconfig.mir
    A llvm/test/CodeGen/X86/AMX/amx-fastpreconfig.mir
    M llvm/test/CodeGen/X86/AMX/amx-zero-config.ll
    M llvm/test/CodeGen/X86/O0-pipeline.ll

  Log Message:
  -----------
  [X86][AMX] Multiple configure for AMX register.

The previous solution depends on variable name to record the shape
information. However it is not reliable, because in release build
compiler would not set the variable name. It can be accomplished with an
additional option `fno-discard-value-names`, but it is not acceptable
for users.
This patch is to preconfigure the tile register with machine
instruction. It follow the same way what sigle configure does. In the
future we can fall back to multiple configure when single configure
fails due to the shape dependency issue.
The algorithm to configure the tile register is simple in the patch. We
may improve it in the future. It configure tile register based on basic
block. Compiler would spill the tile register if it live out the basic
block. After the configure there should be no spill across tile
confgiure in the register alloction. Just like fast register allocation
the algorithm walk the instruction in reverse order. When the shape
dependency doesn't meet, it insert ldtilecfg after the last instruction
that define the shape.
In post configuration compiler also walk the basic block to collect the
physical tile register number and generate instruction to fill the stack
slot for the correponding shape information.
TODO: There is some following work in D125602. The risk is modifying the
fast RA may cause regression as fast RA is usded for different targets.
We may create an independent RA for tile register.

Differential Revision: https://reviews.llvm.org/D125075