[all-commits] [llvm/llvm-project] aa9acb: [InstCombine] add tests for icmp + sub patterns; NFC

[Sanjay Patel via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: aa9acb51f69a862547699c5f7fa5c6f6c1353253
      https://github.com/llvm/llvm-project/commit/aa9acb51f69a862547699c5f7fa5c6f6c1353253
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2022-05-22 (Sun, 22 May 2022)

  Changed paths:
    M llvm/test/Transforms/InstCombine/icmp-range.ll

  Log Message:
  -----------
  [InstCombine] add tests for icmp + sub patterns; NFC


  Commit: 4069cccf3b4ff4afb743d3d371ead9e2d5491e3a
      https://github.com/llvm/llvm-project/commit/4069cccf3b4ff4afb743d3d371ead9e2d5491e3a
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2022-05-22 (Sun, 22 May 2022)

  Changed paths:
    M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
    M llvm/test/Transforms/InstCombine/icmp-range.ll

  Log Message:
  -----------
  [InstCombine] fold icmp with sub and bool

This is the specific pattern seen in #53432, but it can be extended
in multiple ways:
1. The 'zext' could be an 'and'
2. The 'sub' could be some other binop with a similar ==0 property (udiv).

There might be some way to generalize using knownbits, but that
would require checking that the 'bool' value is created with
some instruction that can be replaced with new icmp+logic.

https://alive2.llvm.org/ce/z/-KCfpa


Compare: https://github.com/llvm/llvm-project/compare/e547b04d5b2c...4069cccf3b4f