[all-commits] [llvm/llvm-project] 9af56c: [AMDGPU] Mark SMEM cache invalidations as not read...

[Jay Foad via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9af56c676e40efa551e899675e902cbb3f0db0b6
      https://github.com/llvm/llvm-project/commit/9af56c676e40efa551e899675e902cbb3f0db0b6
  Author: Jay Foad <jay.foad at amd.com>
  Date:   2022-05-20 (Fri, 20 May 2022)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SMInstructions.td
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.vol.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.vol.ll

  Log Message:
  -----------
  [AMDGPU] Mark SMEM cache invalidations as not reading memory

This brings the MachineInstrs in line with the corresponding intrinsics
which have side effects but do not access memory. It also matches how
BUF cache invalidation instructions are defined.

The lit test changes are just because the machine scheduler previously
treated them like loads, and added an artificial scheduling edge from
them to the exit SU, which caused them to be scheduled earlier.

Differential Revision: https://reviews.llvm.org/D126074