[all-commits] [llvm/llvm-project] 602f81: [AArch64] Fix zero element TBL indices

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 602f81ec336330f97e22442b98035c6f007cac6d
      https://github.com/llvm/llvm-project/commit/602f81ec336330f97e22442b98035c6f007cac6d
  Author: David Green <david.green at arm.com>
  Date:   2022-05-19 (Thu, 19 May 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll

  Log Message:
  -----------
  [AArch64] Fix zero element TBL indices

A TBL instruction will fill out-of-range values with 0's, something used
in D121139 to turn tbl2 with a zero input into tbl1s. This works OK for
v16i8, but for v8i8 the input is still treated as a v16i8, so
out-of-range values (like a lane index of 8) would end up loading values
from the top half of the input register. Clean this up by detecting the
out of range values and making sure they really use out of range values.
There is a fix for swapped indices of 64bit input vectors too, which
could be incorrectly adjusted if the zerovector was the first operand.

Fixes #55545

Differential Revision: https://reviews.llvm.org/D125865