[all-commits] [llvm/llvm-project] 615255: [RISCV] Add a test case where mutation still viola...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 615255eb0969a192bebc8ba88dbeb674b5078ee7
      https://github.com/llvm/llvm-project/commit/615255eb0969a192bebc8ba88dbeb674b5078ee7
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2022-05-18 (Wed, 18 May 2022)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll

  Log Message:
  -----------
  [RISCV] Add a test case where mutation still violates strict asserts in InsertVSETVLI

This is the test which triggered my disabling of the assert in d4545e6.  The
issue it reveals is basically the same as from cc0283a6, but in the cross
block case.

We visit block1, mutate the setvli (correctly), and then visit block two and
ask whether the vadd is compatible with the block state.  Before mutation, it
wasn't.  After mutation, it is.  And thus, we have our phase 1 vs 3 difference.