[all-commits] [llvm/llvm-project] 46eef7: [DAGCombiner] Fix bug in MatchBSwapHWordLow.

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 46eef7687639eca1319a93d93d9e588ee0219f8c
      https://github.com/llvm/llvm-project/commit/46eef7687639eca1319a93d93d9e588ee0219f8c
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-05-18 (Wed, 18 May 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/AArch64/arm64-rev.ll
    M llvm/test/CodeGen/ARM/rev.ll
    M llvm/test/CodeGen/RISCV/bswap-bitreverse.ll
    M llvm/test/CodeGen/Thumb/rev.ll
    M llvm/test/CodeGen/X86/bswap.ll

  Log Message:
  -----------
  [DAGCombiner] Fix bug in MatchBSwapHWordLow.

This function tries to match (a >> 8) | (a << 8) as (bswap a) >> 16.

If the SRL isn't masked and the high bits aren't demanded, we still
need to ensure that bits 23:16 are zero. After the right shift they
will be in bits 15:8 which is where the important bits from the SHL
end up. It's only a bswap if the OR on bits 15:8 only takes the bits
from the SHL.

Fixes PR55484.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D125641