[all-commits] [llvm/llvm-project] d4545e: Revert "[RISCV] Enable strict assertions in Insert...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d4545e6fa0366718c2416d3578dd4e1f26855c29
      https://github.com/llvm/llvm-project/commit/d4545e6fa0366718c2416d3578dd4e1f26855c29
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2022-05-17 (Tue, 17 May 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

  Log Message:
  -----------
  Revert "[RISCV] Enable strict assertions in InsertVSETVLI data flow"

This reverts commit 79a66ec97b4fb8cbc4e0a81ead356caf5507a6ea.

The stronger asserts served their purpose; I stumbled across another bug.  Will reapply once this one is also fixed.

The bug appears to be a variant of a previous one:
* We mutate an instruction in one block.
* That mutation changes the phase3 results of another block.

This is very similiar to a previous issue, except cross block instead of within a single block.