[all-commits] [llvm/llvm-project] 79a66e: [RISCV] Enable strict assertions in InsertVSETVLI ...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 79a66ec97b4fb8cbc4e0a81ead356caf5507a6ea
      https://github.com/llvm/llvm-project/commit/79a66ec97b4fb8cbc4e0a81ead356caf5507a6ea
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2022-05-17 (Tue, 17 May 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

  Log Message:
  -----------
  [RISCV] Enable strict assertions in InsertVSETVLI data flow

These asserts are believed to hold after several recent miscompiles have been fixed.  If you see an assertion failure on this change, please toggle the default back and make sure you file a bug with a reproducer.  We may have as yet uncaught miscompiles lurking in this code.

Differential Revision: https://reviews.llvm.org/D125271