[all-commits] [llvm/llvm-project] d40b7f: [DAG] Fold (shl (srl x, c), c) -> and(x, m) even i...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d40b7f0d5aec3b70bd2a5d42c71b1ebb5c28a03b
      https://github.com/llvm/llvm-project/commit/d40b7f0d5aec3b70bd2a5d42c71b1ebb5c28a03b
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2022-05-17 (Tue, 17 May 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/load-lo16.ll
    M llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
    M llvm/test/CodeGen/ARM/combine-movc-sub.ll
    M llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
    M llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
    M llvm/test/CodeGen/RISCV/rvv/legalize-load-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/legalize-store-sdnode.ll
    M llvm/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll

  Log Message:
  -----------
  [DAG] Fold (shl (srl x, c), c) -> and(x, m) even if srl has other uses

If we're using shift pairs to mask, then relax the one use limit if the shift amounts are equal - we'll only be generating a single AND node.

AArch64 has a couple of regressions due to this, so I've enforced the existing one use limit inside a AArch64TargetLowering::shouldFoldConstantShiftPairToMask callback.

Part of the work to fix the regressions in D77804

Differential Revision: https://reviews.llvm.org/D125607