[all-commits] [llvm/llvm-project] 5d29d7: [AArch64] Predicate SSHLL; SCVTF patterns behind Us...

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5d29d752735e71b73a54bfc9ab747384be9e4246
      https://github.com/llvm/llvm-project/commit/5d29d752735e71b73a54bfc9ab747384be9e4246
  Author: David Green <david.green at arm.com>
  Date:   2022-05-16 (Mon, 16 May 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/test/CodeGen/AArch64/arm64-scvt.ll
    M llvm/test/CodeGen/AArch64/int-to-fp-no-neon.ll

  Log Message:
  -----------
  [AArch64] Predicate SSHLL;SCVTF patterns behind UseAlternateSExtLoadCVTF32

There have been some patterns in the AArch64 backend to optimize code of
the form:
  ldrsh w8, [x0]
  scvtf s0, w8
to:
  ldr h0, [x0]
  sshll v0.4s, v0.4h, #0
  scvtf s0, s0
The idea is to remove the GRP->FPR move, but in reality is making code
larger and slower (or the same) on all the cpus I tried.

This patch adds the UseAlternateSExtLoadCVTF32 predicate similar to
nearby related pattern.

Differential Revision: https://reviews.llvm.org/D125470