[all-commits] [llvm/llvm-project] 4c3e51: [AArch64] Handle 64bit vectors in tryCombineFixedP...

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4c3e51ecfa3337be2d091392d6174449aeb35aa3
      https://github.com/llvm/llvm-project/commit/4c3e51ecfa3337be2d091392d6174449aeb35aa3
  Author: David Green <david.green at arm.com>
  Date:   2022-05-16 (Mon, 16 May 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/arm64-fixed-point-scalar-cvt-dagcombine.ll

  Log Message:
  -----------
  [AArch64] Handle 64bit vectors in tryCombineFixedPointConvert

Under some situations we can visit 64bit vector extract elements in
tryCombineFixedPointConvert, where an assert fires as they are expected
to have been converted to 128bit. Turn the assert into an if statement,
bailing out and letting the extract be handled first.

Also invert some ifs, using early exits to reduce indentation.

Fixes #55417