[all-commits] [llvm/llvm-project] 05c3fe: [FastISel] Fix load folding for registers with fixups

[Nikita Popov via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 05c3fe075d608a3e14f6ab272a24132912ebc861
      https://github.com/llvm/llvm-project/commit/05c3fe075d608a3e14f6ab272a24132912ebc861
  Author: Nikita Popov <npopov at redhat.com>
  Date:   2022-05-16 (Mon, 16 May 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
    A llvm/test/CodeGen/X86/fast-isel-load-bitcast-fold.ll

  Log Message:
  -----------
  [FastISel] Fix load folding for registers with fixups

FastISel tries to fold loads into the single using instruction.
However, if the register has fixups, then there may be additional
uses through an alias of the register.

In particular, this fixes the problem reported at
https://reviews.llvm.org/D119432#3507087. The load register is
(at the time of load folding) only used in a single call instruction.
However, selection of the bitcast has added a fixup between the
load register and the cross-BB register of the bitcast result.
After fixups are applied, there would now be two uses of the load
register, so load folding is not legal.

Differential Revision: https://reviews.llvm.org/D125459