[all-commits] [llvm/llvm-project] 1ecc3d: [DAG] Enable ISD::SHL SimplifyMultipleUseDemandedB...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1ecc3d86ae3eeb43336c27c4d653e06236b918a2
      https://github.com/llvm/llvm-project/commit/1ecc3d86ae3eeb43336c27c4d653e06236b918a2
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2022-05-14 (Sat, 14 May 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
    M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
    M llvm/test/CodeGen/Mips/urem-seteq-illegal-types.ll
    M llvm/test/CodeGen/RISCV/rv32zbp.ll
    M llvm/test/CodeGen/RISCV/rv64zbp.ll
    M llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
    M llvm/test/CodeGen/RISCV/vec3-setcc-crash.ll
    M llvm/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll
    M llvm/test/CodeGen/Thumb2/mve-fptosi-sat-vector.ll
    M llvm/test/CodeGen/Thumb2/mve-fptoui-sat-vector.ll
    M llvm/test/CodeGen/X86/load-local-v3i129.ll
    M llvm/test/CodeGen/X86/mul128.ll
    M llvm/test/CodeGen/X86/udiv_fix_sat.ll

  Log Message:
  -----------
  [DAG] Enable ISD::SHL SimplifyMultipleUseDemandedBits handling inside SimplifyDemandedBits

Pulled out of D77804 as its going to be easier to address the regressions individually.

This patch allows SimplifyDemandedBits to call SimplifyMultipleUseDemandedBits in cases where the source operand has other uses, enabling us to peek through the shifted value if we don't demand all the bits/elts.

The lost RISCV gorc2 fold shouldn't be a problem - instcombine would have already destroyed that pattern - see https://github.com/llvm/llvm-project/issues/50553

Differential Revision: https://reviews.llvm.org/D124839