[all-commits] [llvm/llvm-project] af5e09: [RISCV] Add llvm.read.register support for vlenb

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: af5e09b7d9646861863807d8d70e4e672505544e
      https://github.com/llvm/llvm-project/commit/af5e09b7d9646861863807d8d70e4e672505544e
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2022-05-13 (Fri, 13 May 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
    M llvm/test/CodeGen/RISCV/get-register-noreserve.ll

  Log Message:
  -----------
  [RISCV] Add llvm.read.register support for vlenb

This patch adds minimal support for lowering an read.register intrinsic with vlenb as the argument. Note that vlenb is an implementation constant, so it is never allocatable.

This was split off a patch to eventually replace PseudoReadVLENB with a COPY MI because doing so revealed a couple of optimization opportunities which really seemed to warrant individual patches and tests. To write those patches, I need a way to write the tests involving vlenb, and read.register seemed like the right testing hook.

Differential Revision: https://reviews.llvm.org/D125552