[all-commits] [llvm/llvm-project] 7dfc56: [RISCV] Add the passthru operand for RVV unmasked ...
Zakk Chen via All-commits
all-commits at lists.llvm.org
Fri May 13 02:17:14 PDT 2022
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: 7dfc56c10746faeb5759da9ece3d62db06b88511
https://github.com/llvm/llvm-project/commit/7dfc56c10746faeb5759da9ece3d62db06b88511
Author: Zakk Chen <zakk.chen at sifive.com>
Date: 2022-05-13 (Fri, 13 May 2022)
Changed paths:
M clang/include/clang/Basic/riscv_vector.td
M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg_mf.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg_mf.c
M clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg.c
M clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mask.c
M clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mask_mf.c
M clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mf.c
M clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c
M clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics/vlsseg.c
M clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg.c
M clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask.c
M clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask_mf.c
M clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mf.c
M llvm/include/llvm/IR/IntrinsicsRISCV.td
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
M llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
M llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll
M llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll
M llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vlseg2ff-rv32-readvl.ll
M llvm/test/CodeGen/RISCV/rvv/vlseg2ff-rv64-readvl.ll
M llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll
M llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll
M llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll
Log Message:
-----------
[RISCV] Add the passthru operand for RVV unmasked segment load IR intrinsics.
The goal is support tail and mask policy in RVV builtins.
We focus on IR part first.
If the passthru operand is undef, we use tail agnostic, otherwise
use tail undisturbed.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D125323
More information about the All-commits
mailing list