[all-commits] [llvm/llvm-project] ba1c70: [MIPS] Remove an incorrect microMIPS instruction a...

[sdardis via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ba1c70c69db853485c3f286f470a2efc9a4b7fea
      https://github.com/llvm/llvm-project/commit/ba1c70c69db853485c3f286f470a2efc9a4b7fea
  Author: Simon Dardis <simon.dardis at gmail.com>
  Date:   2022-05-11 (Wed, 11 May 2022)

  Changed paths:
    M llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
    M llvm/lib/Target/Mips/MicroMipsInstrInfo.td
    M llvm/lib/Target/Mips/MipsBranchExpansion.cpp
    M llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
    M llvm/lib/Target/Mips/MipsInstrInfo.cpp
    M llvm/lib/Target/Mips/MipsInstrInfo.h
    M llvm/test/CodeGen/Mips/delay-slot-filler-bundled-insts-def-use.mir
    M llvm/test/CodeGen/Mips/delay-slot-filler-bundled-insts.mir
    M llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromips.mir
    M llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mips.mir
    M llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mipsr6.mir
    M llvm/test/CodeGen/Mips/longbranch/branch-limits-int-microMIPS.mir
    M llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mips64.mir
    M llvm/test/CodeGen/Mips/longbranch/branch-limits-int-mips64r6.mir
    M llvm/test/CodeGen/Mips/longbranch/branch-limits-int.mir
    M llvm/test/CodeGen/Mips/longbranch/branch-limits-msa.mir

  Log Message:
  -----------
  [MIPS] Remove an incorrect microMIPS instruction alias

The microMIPS instruction set is compatible with the MIPS instruction
set at the assembly level but not in terms of encodings. `nop` in
microMIPS is a special case as it has the same encoding as `nop` for
MIPS.

Fix this error by reducing the usage of NOP in the MIPS backend such
that only that ISA correct variants are produced.

Differential Revision: https://reviews.llvm.org/D124716